The present invention relates to package design of semiconductor devices.
How to increase a high degree of integration in semiconductor devices is always important in aiming for lighter weight and more compact designs for electronic devices using semiconductor devices such as terminal devices in mobile communication systems (mobile telephone devices). Until now, as many circuits as possible have been combined into a single chip as miniaturization of semiconductor circuits has proceeded apace, and the advantages of miniaturization of mounting surfaces, greater speeds, and lower energy consumption have been put to use. However, the problems of rapidly rising manufacturing costs brought about by miniaturization of semiconductor circuits and longer design and development times have come to the surface.
Accordingly, SIP (System In Package) technology, with which a plurality of semiconductor chips is mounted in three dimensions, has received attention. For example, “Part One: If Chips Don't Work, There's the Package” in “Nikkei Electronics” 2002, 2-11, no. 815, p. 108, describes mounting a semiconductor bare chip 30 on a package substrate 10, further mounting another semiconductor bare chip 31 on the semiconductor bare chip 30, and wire bonding these semiconductor bare chips 30 and 31 to the package substrate 10 with a wire 60, as shown in FIG. 13.
A semiconductor device can be made smaller by placing a plurality of semiconductor chips in a single package, but at the same time this invites a drop in the non-defect ratio (yield). In other words, the non-defect ratio of an SIP is the value of the non-defect ratios of each semiconductor chip multiplied. For example, the non-defect ratio of an SIP with three semiconductor chips, each having a non-defect ratio of 80%, drops to approximately 50% (=0.8×0.8×0.8).
In particular, the non-defect ratio of low-price chips such as DRAMs is lower than the non-defect ratio of logic semiconductor chips such as high-price CPUs, which has led to a problem in that high-price semiconductor chips have been wasted because of defects in low-price semiconductor chips. Accordingly, it is highly desirable that semiconductor chips mounted on SIPs be semiconductor chips which have undergone inspection ahead of time and been verified to be non-defective (“KGD: Known-Good-Die”—inspected, non-defective chips).
Next, a method for achieving KGDs is described. First, a prescribed probe test is performed on each semiconductor chip while still in a wafer. The semiconductor wafer is diced (cut) and the individual semiconductor chips are separated. The semiconductor chips are sorted based on the results of the probe test, and a screening test, such as a burn-in test is further performed on the semiconductor chips which passed the probe test. At this time, the following procedure is performed: the semiconductor chips to be tested are placed in a chip tray or carrier socket for the burn-in test, the burn-in test is performed on the chips using special KGD fixtures and apparatuses, the semiconductor chips are removed from the chip tray or carrier socket for the burn-in test, and only non-defective semiconductor chips are moved to a tray for shipping.
The individual semiconductor chips (bare chips) are formed extremely thinly, meaning they break easily, and extremely sensitive operation is demanded when operating sockets, probes, and testers used in the sorting test.
Japanese Laid-Open Patent Publication No. 2002-40095, for example, discloses a method to resolve these problems.
The semiconductor device disclosed in Japanese Laid-Open Patent Publication No. 2002-40095 is characterized in that an electrode formed on a surface of a first resin-sealed package formed by sealing a semiconductor chip in resin is connected to an electrode of the semiconductor chip and in that a mounting area connected to a mounting object and a testing area for connecting testing equipment are provided. FIG. 14 shows an example of a case in which the semiconductor device disclosed in Japanese Laid-Open Patent Publication No. 2002-40095 is applied to an SIP, and a description follows below with reference to this.
As shown in FIG. 14, a semiconductor package 20 is such that, when mounted on a package substrate 10, a semiconductor package 21 and a semiconductor package 22 are mounted on a lead frame connected to an electrode on the package substrate 10 and sealed in resin by sealing resin 80. At this time, the semiconductor package 21 and the semiconductor package 22 contain a semiconductor bare chip 30 and a semiconductor bare chip 31, respectively, and are each resin-sealed by sealing resin 81. However, when applying the semiconductor devices disclosed in Japanese Laid-Open Patent Publication No. 2002-40095 to an SIP, an electrode 40 of the semiconductor package 21 is connected by a wire 60 to an electrode 41 on the semiconductor 22 on which the semiconductor package 21 is mounted. Further, the electrode 41 on the semiconductor package 22 and the lead frame are connected by a wire 61. The resin-sealed package disclosed in Japanese Laid-Open Patent Publication No. 2002-40095 (the semiconductor package 21 and the semiconductor package 22) is simpler to use than conventional bare chips because it is resin-sealed, and has the effect of reducing the degree of sensitivity demanded in operation of sockets, probes, and testers used in sorting tests.
Further, Japanese Laid-Open Patent Publication No. 2002-40095 is configured such as to eliminate using electrodes damaged by sorting tests during mounting, as the electrodes are separated into electrodes for testing and electrodes for mounting. The following demands are placed on the electrodes for testing and the electrodes for mounting.
First, with regard to the electrodes for testing, the electrode pitch is set to approximately 0.8 mm in, for example, a BGA-type package. If an electrode pitch of this level can be realized, the degree of sensitivity demanded in operation of sockets, probes, and testers used in sorting tests is sufficient at the level of measuring CSPs. On the other hand, with respect to the electrodes for mounting, making the electrode pitch the same as the electrode pitch of ordinary bare chips allows maximum effectiveness. This pitch is, for example, approximately 130 μm. If an electrode pitch of this level can be realized, assembly apparatuses and so on can be used without any particular changes.
A method is disclosed in Japanese Laid-Open Patent Publication No. 2003-249606 which uses an interposer using a glass substrate in order to allow wiring even with the narrow pitch for mounting, described above. However, endowing the arrangement of electrodes for testing and the arrangement of electrodes for mounting with greater freedom faced the problem of an inability to realize user-defined arrangements of electrodes for testing and arrangements of electrodes for mounting, because simply being able to wire even with narrow pitches had a limit.
On the other hand, Japanese Laid-Open Patent Publication No. 2001-196529 provides a wiring method which allows connecting pad electrodes on a semiconductor chip to arbitrary electric connecting portions. FIG. 15 shows the wiring method disclosed in Japanese Laid-Open Patent Publication No. 2001-196529. In FIG. 15, a pad electrode disposed in the vicinity of an edge in the direction of the Y-Y′ arrow of a semiconductor bare chip 30 and a pad electrode disposed in the vicinity of an edge in the direction of the X-X′ arrow of a package substrate 10 are connected via internal wiring of a semiconductor bare chip 31.
A SIP is realized as described above, but in order to realize a chip-on-chip design in which a plurality of chips is stacked in three dimensions, gaps must be provided in the stacked chips. These gaps act to dissipate heat from semiconductor elements and to protect semiconductor elements during mounting. Further, in a case in which the sizes of the stacked chips are the same or approximately the same, these gaps act to prevent bonding pad portions of lower chips from becoming hidden and unable to be wire bonded when the chips are directly stacked. Means for providing these gaps between stacked chips are known as spacers.
In light of the foregoing issues, the object of the present invention is in providing a structure for easily realizing a semiconductor package constituted by mounting in three dimensions semiconductor bare chips which have been certified as KGD.